Dr Sajan P Philip - Bannari Amman Institute of Technology

Degree	Specialization	Institute	University	Year of Passing
B.Tech	Electronics and Communication Engineering	College of Engineering Chengannur Kerala	Cochin University of Science & Technology, Kochi	2010
M.E	Applied Electronics	Bannari Amman Institute of Technology	Cochin University of Science & Technology, Kochi	2013
Ph.D	Applied Electronics	Dr NGP Institute of Technology -Coimbatore	Anna University, Chennai	2022

Elango, S., Sampath, P., Philip, S. P., & Raj, A. D. (2023). Design of unsigned 2n+ 1 parallel residue arithmetic multiplier. AIP Conference Proceedings, 2725, 040006. AIP Publishing LLC.

Elango, S., Sampath, P., Raja Sekar, S., Philip, S. P., & Daniel Raj, A. (2023). High-Performance Multi-RNS assisted Concurrent RSA Cryptosystem Architectures. Journal of Circuits, Systems and Computers.
Elango, S., Sampath, P., Philip, S. P., & Sekar, S. R. (2021). Modelling of Parallel Unsigned 2n-1 Modular Arithmetic Multiplier for RNS. IOP Conference Series: Materials Science and Engineering, 1084, 012060. IOP Publishing.

Sekar, E., Palaniswami, S., Philip, S. P., Gavaskar, K., Danielraj, A., & Others. (2021). Design of Reconfigurable Signed Dual Modulo Multiplier Function (DMMF) for RNS. 2021 Smart Technologies, Communication and Robotics (STCR), 1–5. IEEE.

Sekar, S. R., Elango, S., Philip, S. P., & Raj, A. D. (2021). FPGA Implementation of ECC Enabled Multi-factor Authentication (E-MFA) Protocol for IoT Based Applications. Microelectronic Devices, Circuits and Systems: Second International Conference, ICMDCS 2021, Vellore, India, February 11-13, 2021, Revised Selected Papers 2, 430–442. Springer Singapore.

Elango, S., Sampath, P., Sekar, S. R., & Philip, S. P. (2021). High-Performance Residue Arithmetic Based Elliptic Curve Cryptosystem Over GF (p) for Hardware Security. Microelectronic Devices, Circuits and Systems: Second International Conference, ICMDCS 2021, Vellore, India, February 11-13, 2021, Revised Selected Papers 2, 451–466. Springer Singapore.

Philip, S. P., Palaniswami, S., & Sivakumar, H. (2020). A computationally efficient 11 band non-uniform filter bank for hearing aids targeting moderately sloping sensorineural hearing loss. Informacije MIDEM, 50(3), 153–168.

Elango, S., Sampath, P., Ali, K. S., Philip, S. P., & Raj, A. D. (2018). Investigation and VLSI Implementation of Linear Convolution Architecture For FPGA Based Signal Processing Applications. International Journal of Pure and Applied Mathematics, 119(162018), 4607–4624.

Jacob, F. M., Philip, S. P., & Dinesh, T. (2015). Design and implementation of an Embedded Linux based application for realtime Digital Video Recording subsystem. International Journal of Advanced Research in Computer Engineering & Technology (IJARCET), 4(1).

Philip, S. P., Prakash, S. P., & Valarmathy, S. (2013). An Efficient Decision Tree Based Architecture for Random Impulse Noise Removal in images. International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, 2(4), 1616–1623.

Philip, S. P., Prakash, S. P., & Valarmathi, S. (2013). Design of Efficient Complementary Pass Transistor based Modified Booth Encoder Array Multiplier. International Journal of Computer Applications, 64(5).

Sajan P Philip, “Machine Learning Based Contactless Attendance Monitoring System For Covid-19”, Second International Conference on “Artificial Intelligence and Smart Computing (ICAISC – 2022 Virtual Conference)”, BIT, 2022.

Sajan P Philip, IOT Based Water Purification & Monitoring “International Conference on “Second International Conference on Artificial Intelligence and Smart Computing (ICAISC – 2022 Virtual Conference)”, BIT, 2022.

Sajan P Philip, R. Nandhini, “Performance Improvement and VLSI Implementation of Digital hearing aid architecture using Multi Dimensional Logarithmic Number System”, CENT, Department of ECE, Kongu Engineerin College, Erode, January 2018

Sajan P Philip, Devakumar P V, “Design of a Multiplier Unit using Logarithmic Number System”, Kongu Engineering College, Erode, January 2017

Sajan P. Philip, S P Prakash, Dr. S Valarmathy, “Design of an efficient Impulse Noise Detector Architecture using Decision Tree Based Denoising Method” Recent Advances In Power Electronics And Industrial Drives (PEID 2013)”, IECTE, Info Institute of Engineering, Coimbatore, Coimbatore, November 2013

Sajan P.P Philip, S.P.Prakash, Dr.S.Valarmathy, “An efficient Hardware architecture based on DTBD Method for Random Impulse Noice Detection in Images”, Innovation in intelligent Instrumentation, Optimization and signal Processing (2013), ECE Department, Karunya University, Coimbatore, January 2013

Sajan P. Philip, S P Prakash, Dr. S Valarmathy, “An Efficient Hardware architecture based on DTBD Method for Random Impulse Noise Detection in Images”, International Conference on Intelligent Instrumentation, Optimization and Signal Processing (2013), Karunya University, Coimbatore., December 2012